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引用本文:吴兵,夏浩淼,李武建. 一种超宽带等效采样接收机的设计与实现[J]. 雷达科学与技术, 2017, 15(4): 443-448.[点击复制]
WU Bing, XIA Haomiao, LI Wujian. Design and Implementation of Ultra-Wideband Equivalent Sampling Receiver[J]. Radar Science and Technology, 2017, 15(4): 443-448.[点击复制]
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一种超宽带等效采样接收机的设计与实现
吴兵,夏浩淼,李武建
中国电子科技集团公司第三十八研究所
摘要:
脉冲超宽带雷达回波信号由于带宽大而难以直接采样,通常采用等效时间采样方法来进行模数转换。传统的等效采样接收机大都是基于改变ADC采样时钟的时延来实现等效采样,采样时钟对触发信号会产生亚稳态时序,不可避免地会出现数据误对齐,必须添加辅助的在线或离线校正设计。针对这一问题,设计了一种基于FPGA内置延迟线的超宽带等效采样接收机,FPGA产生延时可调的发射触发信号去控制波形产生系统,基于高速采样保持器和ADC完成回波接收,实现了超宽带射频信号的等效采样,而无数据误对齐问题。接收机的等效采样速率为12.8GS/s,-3dB采样带宽为6.4GHz,满足脉冲超宽带雷达的应用需求。
关键词:  等效采样  数字延迟线  数字接收机  采样保持器
DOI:
分类号:
基金项目:
Design and Implementation of Ultra-Wideband Equivalent Sampling Receiver
WU Bing, XIA Haomiao, LI Wujian
The 38th Research Institute of China Electronics Technology Group Corporation
Abstract:
It is hard to directly sample the ultra-wideband radar echoes due to its large bandwidth.The equivalent time sampling method is often used to carry out analog to digital conversion(ADC).Traditional equivalent sampling receivers are mostly based on changing the delay of ADC sampling clock to realize equivalent sampling.Due to the metastable state between sampling clock and trigger signal, the received data is misaligned inevitably and the correction algorithm online or offline must be added.To solve this problem, an ultra-wideband equivalent sampling receiver based on internal delay line of FPGA is designed.Based on the received echoes of high speed sample-and-hold and ADC, the equivalent sampling of ultra-wideband RF signal is realized without data misaligning when using the delay-tunable transmitting signal generating by FPGA to control the waveform generating system.The equivalent sampling rate is 12.8GS/s and -3dB sampling bandwidth is 6.4GHz, meeting the application requirements of UWB radar.
Key words:  equivalent sampling  digital delay line  digital receiver  sample-and-hold

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