基于FPGA的微型SAR成像信号处理技术

胡晓琛; 李威; 朱岱寅; 崔爱欣

引用本文:	胡晓琛，李威，朱岱寅，崔爱欣. 基于FPGA的微型SAR成像信号处理技术[J]. 雷达科学与技术, 2018, 16(2): 145-150.[点击复制]
	HU Xiaochen, LI Wei, ZHU Daiyin, CUI Aixin. MiniSAR Imaging Processing Technique Based on FPGA[J]. Radar Science and Technology, 2018, 16(2): 145-150.[点击复制]

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基于FPGA的微型SAR成像信号处理技术
胡晓琛，李威，朱岱寅，崔爱欣
南京航空航天大学电子信息工程学院，江苏南京211106

摘要:

微型SAR(MiniSAR)成像处理系统通过现场可编程门阵列(Field Programmable Gate Array, FPGA)设计并实现。该系统中成像处理流程以极坐标格式算法(Polar Format Algorithm, PFA)为基础，首先对回波数据进行参考距离补偿，再采用尺度变换原理(Principle of Chirp Scaling, PCS)代替插值过程实现距离向的重采样，能够在提升算法精度的同时，提高运算效率；方位向处理采用高精度的Sinc插值方法，流水线输出插值结果，运算效率进一步提高；最后，系统通过相位梯度自聚焦(Phase Gradient Autofocus，PGA)算法实现残留相位误差的估计和补偿。基于Xilinx公司的Virtex7-XC7VX6907开发板对系统进行了成像处理和验证，系统工作频率为200MHz，在5.10s时间内实现8192×4096个采样点的32位单精度浮点成像处理。实测数据处理结果验证了系统的有效性。

关键词: 微型合成孔径雷达(MiniSAR) 极坐标格式算法(PFA) 现场可编程门阵列(FPGA) 相位梯度自聚焦(PGA)

DOI：10.3969/j.issn.1672-2337.2018.02.005

分类号:TN958

基金项目:国家自然科学基金(No.61671240)；中央高校基本科研业务费(No.NZ2016105)；江苏省普通高校专业学位研究生科研创新计划项目(No.SJZZ160057)；南京航空航天大学研究生创新基地（实验室）开放基金资助项目(No.kfjj20170401)

MiniSAR Imaging Processing Technique Based on FPGA

HU Xiaochen, LI Wei, ZHU Daiyin, CUI Aixin

College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 211106, China

Abstract:

A miniaturized synthetic aperture radar (MiniSAR) imaging system is designed and realized based on field programmable gate array (FPGA). The proposed system relies on the polar format algorithm (PFA) and compensates for the echo data using the reference distance. The principle of chirp scaling (PCS) is applied to replace the traditional interpolation to implement the range resampling, which improves the accuracy and the efficiency of the algorithm. Then, the high precision interpolation kernel via the Sinc function is employed to resample the azimuth signal. The interpolation results are pipeline output, which further enhances the system efficiency. Finally, the phase gradient autofocus (PGA) algorithm is used to estimate and compensate for the remained phase error accurately. Utilizing the Virtex7-XC7VX6907 evaluation board of the Xilinx Company with the clock frequency of 200MHz, the system takes 5.10s to realize the single-precision floating-point image with 8192×4096 pixels. The experimental data demonstrates the validity.

Key words: miniaturized synthetic aperture radar (MiniSAR) polar format algorithm (PFA) field programmable gate array (FPGA) phase gradient autofocus (PGA)