| 摘要: |
| 在机载雷达或电子战接收系统对大带宽数字中频信号的预处理过程中，针对传统并行多相滤波方式存在FPGA乘法器资源消耗过多的缺陷，提出对并行多相分解系数进行快速滤波算法构建，实现高速ADC采样率在4~8 GS/s之间的数字下变频处理。即先将高速中频采样信号解析为并行32支路，再通过数字混频及2倍抽取将基带复信号的并行度降至16，最后基于短卷积算法构建的16相快速滤波架构，实现对高采样率、大带宽信号的数字下变频预处理。通过基于并行16相快速滤波算法的宽带数字下变频设计与应用，将FPGA乘法器资源降至传统并行多相滤波方式的32%左右，大幅节省资源并提升单片FPGA对多通道、高采样率中频信号的预处理能力。 |
| 关键词: 采样率 16相快速滤波 数字下变频 FPGA |
| DOI：DOI:10.3969/j.issn.1672-2337.2024.02.014 |
| 分类号:TN957.5 |
| 基金项目: |
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| Implementation of 4~8 GS/s Intermediate Frequency Sampling Signal Preprocessing with 16⁃Phase Fast Filter |
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WANG Lihua, ZHAO Weiwei
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AVIC Leihua Electronic Technology Research Institute, Wuxi 214063, China
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| Abstract: |
| In the preprocessing of large bandwidth digital intermediate frequency（IF）signals in the airborne radar or electronic warfare receiving system, the traditional parallel polyphase filtering has the drawback of consuming excessive FPGA’s multiplier resource. A method with construction of fast filtering algorithm by parallel polyphase decomposition coefficients is proposed to realize digital down conversion（DDC）processing of high?speed ADC sampling rate between 4 GS/s and 8 GS/s. First, the IF sampling signal is decomposed into 32 parallel branches. Then, the parallelism of the baseband complex signal is reduced to 16 through digital mixing and double decimation. Finally, to realize DDC processing of high sampling rate and large bandwidth signal, the 16?phase fast filtering architecture based on the short convolution algorithm is constructed. Through the design and application of wideband DDC based on 16?phase fast filtering, the FPGA multiplier resource is reduced to about 32% of the traditional parallel polyphase filtering, which greatly saves FPGA’s resource and improves the preprocessing ability of single FPGA for multi?channel and large bandwidth signals. |
| Key words: sampling rate 16⁃phase fast filter digital down conversion FPGA |
